Several trends presently exist in the semiconductor and electronics industry. One of these trends is that recent generations of portable electronic devices are using more memory than previous generations. This increase in memory allows these new devices to store more data, such as music or images, and also provides the devices with more computational power and speed.
One type of memory device includes an array of resistive memory cells, where individual bits of data can be stored in the individual resistive memory cells of the array. Depending on how the cell is biased, it can be switched between a more resistive state or a less resistive state. In real world-implementations, the more resistive state can be associated with a logical “1” and the less resistive state can be associated with a logical “0”, or vice versa. Additional resistive states could also be defined to implement a multi-bit cell with more than two states per cell. Therefore, by switching between the resistive states, a user can store any combination of “1”s and “0”s in the array, which could correspond to digitally encoded music, images, software, etc.
In resistive memories, the characteristics of the memory cells may drift over time. For example, cells that are accessed much more than average may tend to exhibit data failures. Because some applications may not tolerate data errors, the failure of these individual cells seriously limits the failure rate of the memory device. Therefore, a need has arisen to provide systems and methods relating to memory devices that can account for faulty cells.